Higher Order Voronoi Diagrams of Segments for VLSI Critical Area Extraction

We address the problem of computing critical area for open faults in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is a fundamental problem in VLSI yield prediction. We first model the problem as a graph problem and then we solve it efficiently by exploiting its geometric nature. We introduce the open-fault Voronoi diagram of polygonal objects, a generalization of Voronoi diagrams based on concepts of higher order Voronoi diagrams of segments. Once this Voronoi diagram is available the entire critical area integral for open faults can be computed analytically in linear time similarly to [7, 8, 5]. This paper expands the Voronoi critical area computation paradigm [7, 5, 6] with the ability to accurately compute critical area for missing material defects even in the presence of loops and redundant interconnects spanning over multiple layers. Catastrophic yield loss of integrated circuits is caused to a large extent by random particle defects interfering with the manufacturing process resulting in functional failures such as open or short circuits. All yield models for random manufacturing defects focus on critical area, a measure reflecting the sensitivity of the design to random defects during manufacturing (see e.g. [9]). The critical area of a circuit layout on a layer A is defined as